Xilinx Hardware Accelerators Link Up With O

Feb 07, 2024

Just this month, Xilinx unveiled the T1, a new hardware accelerator card designed to offload 5G Open Radio Access Network (O-RAN) fronthaul transport requirements and the computationally-intensive, low-density parity checks (LDPC) in the L1 network stack.

In conjunction with partner-developed IP cores and the O-RAN Alliance, Xilinx says it is optimizing 5G server performance with the T1 PCIe accelerator card. The Xilinx T1 card is an x16 Gen 3 PCIe smart NIC based upon the Zynq Ultrascale+ FPGA and a Zynq RFSoC chipset.

Network virtualization of 5G aggregate data in software has resulted in throughput limitations because the higher data rates defined by the 3GPP can only be overcome with hardware acceleration. Xilinx says its T1 hardware accelerator used alongside a commercial off-the-shelf server results in orders of magnitude higher throughput and reduced latency.

The T1 offloads the two most intensive operations in a radio access network: 1) fronthaul termination between the radio unit and the distributed unit and 2) L1 forward error correction (FEC), hybrid automatic repeat request (HARQ), and other high PHY functions.

Additionally, Xilinx reports 15 to 30 times improvement in ZUC and IPSec algorithms, which are part of the packet data convergence protocol (PDCP).

Jessy Cavazos, writing for Keysight, describes the O-RAN solution as capable of increasing data rates for mobile networks as the 7-2 split.

The 7-2 split breaks up the PHY into a high-PHY and low-PHY (option 7) whose functions are split between the radio unit (O-RU) and the distributed unit (O-DU). Then, the computationally intensive operations (option 2) are carried out by the centralized unit (O-CU) baseband unit where we find the Xilinx T1 accelerator.

In the press release for the accelerator, Xilinx's VP of marketing for the company's wired and wireless group, Dan Mansur, says, “the trend toward network virtualization and O-RAN has given us an opportunity with the Xilinx T1 Telco Accelerator Card to drive the next steps of disaggregation of standard networks, enabling our expansion into every corner of the 5G market."

He explains that the company is collaborating with its ecosystem partners to enhance Xilinx's hardware, IP, and software to lead "the innovation and realization of 5G O-RAN networks.”

The Xilinx Ultrascale+ FPGA ecosystem aligns well with the O-RAN Alliance's objective of open hardware interfaces, which is said to facilitate vendor competition and lead to improved systems and lower cost deployments. The T1 offers pre-loaded industry partner FPGA reference designs, which can interface through the PCIe interface with the industry-standard baseband device (BBDev) API on the open-source FlexRAN x86 user platform.

Hardware acceleration may be the key to actualizing 5G throughput and low-latency targets in radio fronthaul links. General-purpose processors on the network edge are then freed to do the more important commercial tasks of providing streaming, gaming, and automotive services.